Lab 2 Specifications

The lab 2 specifications are trying to get you to focus on two new topics: constructing large Verilog systems by intelligently reusing modules, and clean schematic construction.

Hardware Specifications

Proficiency

• Resistors are in series with FPGA pins so that they correctly limit current
• Scanning signal appears on LEDs when appropriate buttons are depressed on the keypad.

Excellence

• Seven segment displays are same brightness regardless of how many segments are lit
• No noticeable bleeding of the digits between displays
• No flickering on the individual digits
• Scanning signal continues to be displayed under different keypress conditions, including multiple touches on rows or columns (at minimum 2 simultaneous presses).

Verilog Structure and Style Specifications

Proficiency

• HDL design includes only a single seven-segment decoder module that is time multiplexed.
• Top design only includes instances of HSOSC, seven-segment module, multiplexing counter module, scanning module and assign statements to implement multiplexing and scanning passthrough.
• Scanning module only includes instances of a counter and assign statements that convert from the counter output to output values.
• Scanning module is resettable and enable-able.
• No counters implemented inline, all of them are contained in modules.

Excellence

• All counter modules (scanning and multiplexing) are parametrized instances of the counter module from lab 1.

Simulation Specifications

Proficiency

• No repeat simulations from lab 1. Those modules have already been verified!
• QuestaSim simulations carried out (possibly manually) for the scanning module and the top module.
• All simulations captured as legible waveform screenshots in report.

Excellence

• Automatic testbench for the scanning module that demonstrates all four output transitions, enable and reset features.
• Automatic testbench for the top module that exercises multiplexing functionality and LED driving functionality.

Block Diagram Specs

Proficiency and Excellence

• Block diagram exists and a good faith effort was made to follow the specs below. Block diagram specs in full effect in lab 3.

Other Documentation

Proficiency

• Current draw/sink on all FPGA pins are below the currents specified in the recommended operating conditions. Claims are backed up by calculations and reference to the appropriate items on the datasheet.

Excellence

• No errors in the calculations (correct forward voltage read off the datasheet, proper voltages used, etc.)

Schematic Specifications

Proficiency

• All pin names labeled
• All pin numbers labeled
• Crossing wires clearly identified as junction or unconnected
• Neat layout (e.g., clear organization and spacing)
• All parts labeled with part number
• All component values present

Excellence

• Standard symbols used for all components where applicable
• Signals “flow” from left to right where possible (e.g., inputs on left hand side, outputs on right hand side)
• Title block with author name, title, and date

Lab Writeup

Proficiency and Excellence

• Documentation embedded in a well-structured, concise report with one section per major deliverable. Sections should match structure of other specs.
• Spoiler tags are used to hide screenshots and code. Some unspoilered entries (~1 waveform, essential code snippets) allowed if they are essential to the narrative, kept to a minimum.
• Writeup contains minimal spelling or grammar issues and any errors do not significantly detract from clarity of the writeup.
• Statement of whether the design meets all the requirements. If not, list the shortcomings.
• AI prototype attempted and some reflection is recorded.
• Number of hours spent working on the lab are included.
• (Optional) List comments or suggestions on what was particularly good about the assignment or what you think needs to change in future versions.

FOR REFERENCE, NOT YET IN EFFECT

Block Diagram Specifications

Proficiency

• Each module is represented by a block diagram
• Bare logic in all module is represented by appropriately drawn gates.
• Submodules in each module are represented by blocks inside of the instantiating module.
• Submodules have all ports represented by pin symbols on the boundary of the submodule, each with a port name.
• Submodules indicate the name of the module being instantiated and the name of the instance.
• All connections between module ports, logic and submodules are indicated.
• Module ports are represented by pin symbols on the boundary of the module and labeled with port names
• All nets internal to the module are labeled, even when they share a name with a port on a module/submodule boundary.

Excellence

• Appropriate use of bus notation for multi-bit signals (e.g., data[7:0] for an 8-bit bus), including fan-in and fan-out when needed.
• Appropriate use of implicit connections (i.e.: connect-by-label-name) to reduce routing connection
• Block diagram is an exact, 1:1 representation of the Verilog code.