Lab 7 Specifications

Lab 7 is a capstone lab that requires both microcontroller and FPGA design, which exercises most of the learning goals in the course. (Setting you up for SPI communication between the MCU and the FPGA also sets you up for your project.)Because building a working accelerator on real hardware is a significant undertaking on top of a difficult specification, most of the grading weight is on getting the design to simulate correctly against the reference test vectors in the FIPS-197 standard; getting the design running end-to-end on hardware is an excellence-level stretch goal.

Note that no schematic is required for this lab because the design is fully included on the motherboard.

Hardware Specifications

Proficiency

• SPI interconnect between the MCU and FPGA is wired correctly, matching the clock polarity and phase expected by the provided MCU code.

Excellence

• Design fits on the FPGA and completes a full SPI transaction, returning the correct ciphertext computed by the accelerator (not a value hardcoded or precomputed off-chip).
• SPI communication between the MCU and FPGA is displayed on the logic analyzer.

Verilog Structure and Style Specifications

Proficiency

• AES logic is broken into modules for each major step (e.g., SubBytes, ShiftRows, MixColumns, AddRoundKey, KeyExpansion) rather than one monolithic block.
• Control logic is in a separate module from the datapath logic.
• Style conventions from previous labs (module names, descriptive variables, etc.) are still followed. See HDL specs

Excellence

• Timing is correctly managed around the one-cycle latency of the synchronous RAM used for the sbox substitution.
• Finite state machines are implemented in an appropriate form discussed in lecture: canonical, non-canonical, or communicating.

Simulation Specifications

Proficiency

• testbench_aes_core passes, verifying the aes_core module against the FIPS-197 test vector without the SPI link.
• Full system testbench (including the SPI link) passes.
• All simulations captured as legible waveform screenshots in the report.

Block Diagram Specifications

Proficiency

• Each module is represented by a block diagram
• Bare logic in all module is represented by appropriately drawn gates.
• Submodules in each module are represented by blocks inside of the instantiating module.
• Submodules have all ports represented by pin symbols on the boundary of the submodule, each with a port name.
• Submodules indicate the name of the module being instantiated and the name of the instance.
• All connections between module ports, logic and submodules are indicated.
• Module ports are represented by pin symbols on the boundary of the module and labeled with port names
• All nets internal to the module are labeled, even when they share a name with a port on a module/submodule boundary.

Excellence

• Appropriate use of bus notation for multi-bit signals (e.g., data[7:0] for an 8-bit bus), including fan-in and fan-out when needed.
• Appropriate use of implicit connections (i.e.: connect-by-label-name) to reduce routing connection
• Block diagram is an exact, 1:1 representation of the Verilog code.

Lab Writeup

Proficiency and Excellence

• Documentation embedded in a well-structured, concise report with one section per major deliverable. Sections should match structure of other specs.
• Spoiler tags are used to hide screenshots and code. Some unspoilered entries (~1 waveform, essential code snippets) allowed if they are essential to the narrative, kept to a minimum.
• Writeup contains minimal spelling or grammar issues and any errors do not significantly detract from clarity of the writeup.
• Statement of whether the design meets all the requirements. If not, list the shortcomings.
• AI prototype attempted and some reflection is recorded.
• Number of hours spent working on the lab are included.
• (Optional) List comments or suggestions on what was particularly good about the assignment or what you think needs to change in future versions.